CVE-2026-23554 — Use after free of paging structures in EPT

Description (CNA)

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

Affected (CNA)

Vendor / product	Versions
Xen / Xen	unknown consult Xen advisory XSA-480

CWE

No CWE identifiers supplied.

References

https://xenbits.xenproject.org/xsa/advisory-480.html

ADP enrichment

CVE

No English description supplied.

http://www.openwall.com/lists/oss-security/2026/03/17/6
http://xenbits.xen.org/xsa/advisory-480.html

CISA-ADP

No English description supplied.

No references supplied.